Course Abstract Details

ENEE-244, Digital Logic Design

Credits: 3

Course Description

ENEE-244, Digital Logic Design, introduces the basic principles and design procedures of digital systems at the gate and intermediate chip levels for electrical engineering students. The student will acquire knowledge of gates, flip-flops, registers, counters, Karnaugh maps, PAL devices, and synchronous sequential circuit design and analysis. Students will design and analyze combinatorial logic circuits and synchronous sequential circuits. Prerequisite: MATH-130. Three hours lecture each week. Three credits. Three billable hours. Offered Fall term only.

Course Objectives and Grading Information

MAJOR COURSE OBJECTIVES: Upon completion of this course, the student will be able to:

1. Convert between decimal, binary, octal, and hexadecimal number systems. (PG-1) (LG-3)

2. Do two-level logic minimization using Boolean algebra, Karnaugh maps, and the Quine-McCluskey tabular minimization method. (PG-1,2) (LG-2,3)

3. Incorporate medium scale integrated circuits, such as decoders, encoders, and multiplexers, into circuit design. (PG-1,2) (LG-2,3)

4. Use algorithmic state machine notation. (PG-1) (LG-3)

5. Design and analyze clocked sequential circuits. (PG-1,2) (LG-2,3)

6. Build binary memory using various types of latches and flip-flops. (PG-1,2) (LG-2,3)

7. Program PLA, PAL, SPLD devices. (PG-1,2) (LG-2,3)

8. Describe various types of memory parity and error correction algorithms. (PG-1,2) (LG-2,3)

9. Perform asynchronous sequential logic analysis. (PG-1,2) (LG-2,3)

REQUIRED TEXTBOOK(S)
Givone, D.D. Digital Principles and Design with CD-ROM, 1st edition. Mc-Graw Hill, 2003. [ISBN-13: 978-0-07-255132-7]

Learning Goals

The abbreviations in parentheses represent Learning Goals which have been identified for this course and program of study:

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